STA Engineer (M, F, D)
Lex
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Munich, Germany
Posted on May 30, 2026
Summary
We are looking for talented engineers to join our STA team. In this role, you will be working closely with multiple integration teams, like DFT, Top Level PNR, PHY designers and PNR teams.
Description
You will be responsible for:
Developing automated block and full chip level signoff flows
Full Chip Timing/Noise convergence and full signoff for high quality TO
Enabling hierarchical Timing flows
Power optimizations
Generating block level budget and context for correlation with Full Chip
Driving custom IP integration and custom timing checks flows
Closing work with Design, DFT, architecture and Power team
Minimum Qualifications
At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
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Role Number: 200653786-1731
We are looking for talented engineers to join our STA team. In this role, you will be working closely with multiple integration teams, like DFT, Top Level PNR, PHY designers and PNR teams.
Description
You will be responsible for:
Developing automated block and full chip level signoff flows
Full Chip Timing/Noise convergence and full signoff for high quality TO
Enabling hierarchical Timing flows
Power optimizations
Generating block level budget and context for correlation with Full Chip
Driving custom IP integration and custom timing checks flows
Closing work with Design, DFT, architecture and Power team
Minimum Qualifications
- You hold a MSEE or equivalent strong experience in Static Timing analysis
- Extensive experience with one of the commercial STA tools
- Ability to fluently speak and write in English.
- Familiarity with hierarchical design approach, top-down design, timing and physical convergence
- Experience with backend STA closure and Signoff
- Deep understanding of designs' constraints development
- Good understanding of AC timing from specs to implementation
- Good understanding of DFT modes and their constraints
- Good communication skills and team player
- Quick learning of flows and methods
- Advantage - Understanding noise and signal integrity effects
- Advantage - Timing margins fundamental from synthesis to signoff
- Advantage - Experience with scripting
At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
Learn about accessibility in Apple’s workplace
Role Number: 200653786-1731
This job is no longer accepting applications
See open jobs at Lex.See open jobs similar to "STA Engineer (M, F, D)" Tusk Venture Partners.